//################################################################################
// initial date : 2023/2/4 15:16:50
// Author       : Auto-generator Regs RTL tool
// Description  : Instantiate specified Regs.
//################################################################################

module xxx_regs (
input                                       rst_n,      // reset non-configuration regs
input                                       rst_cfg_n,  // reset configuration regs
input                                       clk,

input               [1-1:0]                 fifo_ilf_eis,
output              [1-1:0]                 fifo_ilf_ie,
input               [1-1:0]                 fifo_ilf_ois,
output              [1-1:0]                 fifo_ilf_ois_hst,
input                                       cnt_rx_good_octet_ce,
input               [13-1:0]                cnt_rx_good_octet_inc,
input                                       cnt_rx_cmd_ce,
input                                       cnt_tx_cmd_ce,
output              [1-1:0]                 mem_rw_start,
output              [1-1:0]                 mem_rw_type,
output              [1-1:0]                 mem_rw_b2b,
input                                       mem_rw_addr_bwe,
input               [12-1:0]                mem_rw_addr_bwd,
output              [12-1:0]                mem_rw_addr,
output                                      mem_rw_addr_fwe,
output                                      mem_rw_addr_fre,
input               [1-1:0]                 mem_rw_miss,
input               [1-1:0]                 mem_rw_busy,
input                                       mem_rw_data_bwe,
input               [32-1:0]                mem_rw_data_bwd,
output              [32-1:0]                mem_rw_data,
output                                      mem_rw_data_fwe,
output                                      mem_rw_data_fre,
output              [32-1:0]                disable_cfg,
output                                      disable_cfg_fwe,
input               [1-1:0]                 auto_req_clr,
output              [1-1:0]                 auto_req,
output              [1-1:0]                 phy_reset,
input               [4-1:0]                 link_err,
input               [4-1:0]                 phy_err,
input                                       scnt_wcmd_1berr_ce,
input                                       scnt_rcmd_1berr_ce,
input               [16-1:0]                fifo_cnt_max,
input               [16-1:0]                fifo_cnt_min,
input               [32-1:0]                grp_ext,
output                                      grp_ext_fwe,
output                                      grp_ext_fre,

// Register Access Bus
input                                       rab_en,     // single pulse means a R/W access start
input                                       rab_wr,     // 1'b1: write; 1'b0: read, keep stable until R/W done
input               [12-1:0]                rab_addr,   // keep stable until R/W done
input               [32-1:0]                rab_wdat,   // keep stable until W done
output              [32-1:0]                rab_rdat,   // valid after rab_busy deasserting, and keep stable until next R
output                                      rab_busy    // assert after rab_en fell if rab_rdat is not ready
);

wire                                        we;
wire                                        re;
wire                [14-1:0]                cs_ary;
wire                [14*32-1:0]             rdat_ary;

assign we = rab_en &   rab_wr;
assign re = rab_en & (~rab_wr);

// ********************** ENA_INT_STATUS (0x100) ****************************************
assign cs_ary[0] = (rab_addr==12'h100) ? 1'b1 : 1'b0;
assign rdat_ary[0*32+1+:31] = 31'h0;
assign rdat_ary[0*32+0+:1] = fifo_ilf_eis;

// ********************** INT_ENABLE (0x104) ****************************************
assign cs_ary[1] = (rab_addr==12'h104) ? 1'b1 : 1'b0;
assign rdat_ary[1*32+1+:31] = 31'h0;

rw_reg #(.DW(1), .INI(1'h1)) u_fifo_ilf_ie (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[1]),
    .we         (we),
    .wd         (rab_wdat[0:0]),
    .q          (fifo_ilf_ie)
);
assign rdat_ary[1*32+0+:1] = fifo_ilf_ie;

// ********************** ORG_INT_STATUS (0x108) ****************************************
assign cs_ary[2] = (rab_addr==12'h108) ? 1'b1 : 1'b0;
assign rdat_ary[2*32+1+:31] = 31'h0;

hhl_wc_reg #(.DW(1)) u_fifo_ilf_ois (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[2]),
    .we         (we),
    .wd         (rab_wdat[0:0]),
    .d          (fifo_ilf_ois),
    .q          (fifo_ilf_ois_hst)
);
assign rdat_ary[2*32+0+:1] = fifo_ilf_ois_hst;

// ********************** DFX_CNT (0x120) ****************************************
assign cs_ary[3] = (rab_addr==12'h120) ? 1'b1 : 1'b0;
assign cs_ary[4] = (rab_addr==12'h124) ? 1'b1 : 1'b0;
assign rdat_ary[3*32+40+:24] = 24'h0;

wire [40-1:0] cnt_rx_good_octet;
ccnt_rc_reg #(.IW(13), .DW(32), .CW(40)) u_cnt_rx_good_octet (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[3]),
    .re         (re),
    .ce         (cnt_rx_good_octet_ce),
    .inc        (cnt_rx_good_octet_inc),
    .q          (cnt_rx_good_octet)
);
assign rdat_ary[3*32+0+:40] = cnt_rx_good_octet;

// ********************** CMD_CNT (0x12C) ****************************************
assign cs_ary[5] = (rab_addr==12'h12C) ? 1'b1 : 1'b0;

wire [16-1:0] cnt_rx_cmd;
ccnt_wc_reg #(.IW(1), .DW(32), .CW(16)) u_cnt_rx_cmd (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[5]),
    .re         (re),
    .we         (we),
    .wd         (rab_wdat[16]),
    .ce         (cnt_rx_cmd_ce),
    .inc        (1'd1),
    .q          (cnt_rx_cmd)
);
assign rdat_ary[5*32+16+:16] = cnt_rx_cmd;

wire [16-1:0] cnt_tx_cmd;
ccnt_rc_reg #(.IW(1), .DW(32), .CW(16)) u_cnt_tx_cmd (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[5]),
    .re         (re),
    .ce         (cnt_tx_cmd_ce),
    .inc        (1'd1),
    .q          (cnt_tx_cmd)
);
assign rdat_ary[5*32+0+:16] = cnt_tx_cmd;

// ********************** MEM_RW_CTRL (0x130) ****************************************
assign cs_ary[6] = (rab_addr==12'h130) ? 1'b1 : 1'b0;

w1_pls_reg #(.DW(1)) u_mem_rw_start (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[6]),
    .we         (we),
    .wd         (rab_wdat[31:31]),
    .q          (mem_rw_start)
);
assign rdat_ary[6*32+31+:1] = 1'b0;

rw_reg #(.DW(1), .INI(1'h0)) u_mem_rw_type (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[6]),
    .we         (we),
    .wd         (rab_wdat[30:30]),
    .q          (mem_rw_type)
);
assign rdat_ary[6*32+30+:1] = mem_rw_type;

rw_reg #(.DW(1), .INI(1'h0)) u_mem_rw_b2b (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[6]),
    .we         (we),
    .wd         (rab_wdat[29:29]),
    .q          (mem_rw_b2b)
);
assign rdat_ary[6*32+29+:1] = mem_rw_b2b;
assign rdat_ary[6*32+12+:17] = 17'h0;

bid_rw_reg #(.DW(12), .INI(12'h123)) u_mem_rw_addr (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[6]),
    .re         (re),
    .we         (we),
    .wd         (rab_wdat[11:0]),
    .bwe        (mem_rw_addr_bwe),
    .bwd        (mem_rw_addr_bwd),
    .q          (mem_rw_addr),
    .fwe        (mem_rw_addr_fwe),
    .fre        (mem_rw_addr_fre)
);
assign rdat_ary[6*32+0+:12] = mem_rw_addr;

// ********************** MEM_RW_ST (0x134) ****************************************
assign cs_ary[7] = (rab_addr==12'h134) ? 1'b1 : 1'b0;

wire   [1-1:0] mem_rw_miss_hst;
hhl_wc_reg #(.DW(1)) u_mem_rw_miss (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[7]),
    .we         (we),
    .wd         (rab_wdat[31:31]),
    .d          (mem_rw_miss),
    .q          (mem_rw_miss_hst)
);
assign rdat_ary[7*32+31+:1] = mem_rw_miss_hst;
assign rdat_ary[7*32+1+:30] = 30'h0;
assign rdat_ary[7*32+0+:1] = mem_rw_busy;

// ********************** MEM_RW_DATA (0x138) ****************************************
assign cs_ary[8] = (rab_addr==12'h138) ? 1'b1 : 1'b0;

bid_rw_reg #(.DW(32), .INI(32'h0)) u_mem_rw_data (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[8]),
    .re         (re),
    .we         (we),
    .wd         (rab_wdat[31:0]),
    .bwe        (mem_rw_data_bwe),
    .bwd        (mem_rw_data_bwd),
    .q          (mem_rw_data),
    .fwe        (mem_rw_data_fwe),
    .fre        (mem_rw_data_fre)
);
assign rdat_ary[8*32+0+:32] = mem_rw_data;

// ********************** DISABLE_CFG (0xA00) ****************************************
assign cs_ary[9] = (rab_addr==12'hA00) ? 1'b1 : 1'b0;

rw_pls_reg #(.DW(32), .INI(32'h12345678)) u_disable_cfg (
    .rst_cfg_n  (rst_cfg_n),
    .clk        (clk),
    .cs         (cs_ary[9]),
    .we         (we),
    .wd         (rab_wdat[31:0]),
    .q          (disable_cfg),
    .fwe        (disable_cfg_fwe)
);
assign rdat_ary[9*32+0+:32] = disable_cfg;

// ********************** HST_ERR (0xABC) ****************************************
assign cs_ary[10] = (rab_addr==12'hABC) ? 1'b1 : 1'b0;
assign rdat_ary[10*32+10+:22] = 22'hFF;

rw_sc_reg #(.DW(1)) u_auto_req (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[10]),
    .we         (we),
    .wd         (rab_wdat[9:9]),
    .clr        (auto_req_clr),
    .q          (auto_req)
);
assign rdat_ary[10*32+9+:1] = auto_req;

w1_pls_reg #(.DW(1)) u_phy_reset (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[10]),
    .we         (we),
    .wd         (rab_wdat[8:8]),
    .q          (phy_reset)
);
assign rdat_ary[10*32+8+:1] = 1'b0;

wire   [4-1:0] link_err_hst;
hhl_wc_reg #(.DW(4)) u_link_err (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[10]),
    .we         (we),
    .wd         (rab_wdat[7:4]),
    .d          (link_err),
    .q          (link_err_hst)
);
assign rdat_ary[10*32+4+:4] = link_err_hst;

wire   [4-1:0] phy_err_hst;
hhl_rc_reg #(.DW(4)) u_phy_err (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[10]),
    .re         (re),
    .d          (phy_err),
    .q          (phy_err_hst)
);
assign rdat_ary[10*32+0+:4] = phy_err_hst;

// ********************** SCNT_DFX (0xAC0) ****************************************
assign cs_ary[11] = (rab_addr==12'hAC0) ? 1'b1 : 1'b0;
assign rdat_ary[11*32+6+:26] = 26'h0;

wire [3-1:0] scnt_wcmd_1berr;
scnt_wc_reg #(.IW(1), .DW(32), .CW(3)) u_scnt_wcmd_1berr (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[11]),
    .re         (re),
    .we         (we),
    .wd         (rab_wdat[3]),
    .ce         (scnt_wcmd_1berr_ce),
    .inc        (1'd1),
    .q          (scnt_wcmd_1berr)
);
assign rdat_ary[11*32+3+:3] = scnt_wcmd_1berr;

wire [3-1:0] scnt_rcmd_1berr;
scnt_rc_reg #(.IW(1), .DW(32), .CW(3)) u_scnt_rcmd_1berr (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[11]),
    .re         (re),
    .ce         (scnt_rcmd_1berr_ce),
    .inc        (1'd1),
    .q          (scnt_rcmd_1berr)
);
assign rdat_ary[11*32+0+:3] = scnt_rcmd_1berr;

// ********************** MAX_MIN_DFX (0xAC4) ****************************************
assign cs_ary[12] = (rab_addr==12'hAC4) ? 1'b1 : 1'b0;

wire   [16-1:0] fifo_cnt_max_hst;
max_rc_reg #(.DW(16)) u_fifo_cnt_max (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[12]),
    .re         (re),
    .d          (fifo_cnt_max),
    .q          (fifo_cnt_max_hst)
);
assign rdat_ary[12*32+16+:16] = fifo_cnt_max_hst;

wire   [16-1:0] fifo_cnt_min_hst;
min_rc_reg #(.DW(16)) u_fifo_cnt_min (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[12]),
    .re         (re),
    .d          (fifo_cnt_min),
    .q          (fifo_cnt_min_hst)
);
assign rdat_ary[12*32+0+:16] = fifo_cnt_min_hst;

// ********************** GPR_REG (0xAD0) ****************************************
assign cs_ary[13] = (rab_addr==12'hAD0) ? 1'b1 : 1'b0;

gpr_reg #(.DW(32)) u_grp_ext (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs         (cs_ary[13]),
    .re         (re),
    .we         (we),
    .fwe        (grp_ext_fwe),
    .fre        (grp_ext_fre)
);
assign rdat_ary[13*32+0+:32] = grp_ext;

rdat_mux #(.DW(32), .ALL_NUM(14), .SUB_NUM(256)) U_RDAT_MUX (
    .rst_n      (rst_n),
    .clk        (clk),
    .cs_ary     (cs_ary),
    .rdat_ary   (rdat_ary),
    .re         (re),
    .rbusy      (rab_busy),
    .rdat       (rab_rdat)
);

endmodule
